The Case for Asymmetric Systolic Array Floorplanning<\/h2><\/span>

The widespread proliferation of deep learning applications has triggered the need to accelerate them directly in hardware. General Matrix Multiplication (GEMM) kernels are elemental deep-learning constructs and they inherently map onto Systolic Arrays (SAs). SAs are regular structures that are well-suited for accelerating matrix multiplications. Typical SAs use a pipelined array of Processing Elements (PEs), which communicate with local connections and pre-orchestrated data movements. In this work, we show that the physical layout of SAs should be asymmetric to minimize wirelength and improve energy efficiency. The floorplan of the SA adjusts better to the asymmetric widths of the horizontal and vertical data buses and their switching activity profiles. It is demonstrated that such physically asymmetric SAs reduce interconnect power by 9.1% when executing state-of-the-art CNN layers, as compared to SAs of the same size but with a square (i.e., symmetric) layout. The savings in interconnect power translate, in turn, to 2.1% overall power savings.<\/div><\/div><\/section>\n\n\n\n

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Authors<\/strong><\/span>

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos<\/div><\/div><\/section>\n\n\n\n

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Conference<\/strong><\/strong><\/span>

2023 18th IEEE International Workshop on Cellular Nanoscale Networks and their Applications (CNNA)<\/div><\/div><\/section>\n<\/div>\n\n\n\n

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Availability <\/strong><\/strong><\/strong>Date<\/strong><\/strong><\/strong><\/span>

NA<\/div><\/div><\/section>\n<\/div>\n<\/div>\n\n\n\n

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